Magnetic memories, particularly magnetic random access memories (MRAMs), have drawn increasing interest due to their potential for high read/write speed, excellent endurance, non-volatility and low power consumption during operation. An MRAM can store information utilizing magnetic materials as an information recording medium. One type of MRAM is a spin transfer torque random access memory (STT-RAM). STT-RAM utilizes magnetic junctions written at least in part by a current driven through the magnetic junction. A spin polarized current driven through the magnetic junction exerts a spin torque on the magnetic moments in the magnetic junction. As a result, layer(s) having magnetic moments that are responsive to the spin torque may be switched to a desired state. Conventional STT-RAM is desired to combine the fast read and write speed of SRAM, the capacity and cost benefits of DRAM, and the non-volatility of Flash (zero standby power), coupled with essentially unlimited endurance (for example greater than 1015 cycle). As described below, STT-RAM uses a bi-directional current to write data. Such write operations may be performed without assistance from magnetic field, heat, or other sources of energy. Consequently, STT-RAM may have the lowest writing energy of emerging memory technologies.
For example, FIGS. 1-2 depicts a conventional magnetic tunneling junction (MTJ) 10 as it may be used in a conventional STT-RAM 50. FIG. 1 is a diagram of the conventional MTJ 10, while FIG. 2 depicts the circuit diagram of part of the conventional STT-RAM 50 including the conventional MTJ 10. The conventional MTJ 10 typically resides on a bottom contact 11, uses conventional seed layer(s) 12 and includes a conventional antiferromagnetic (AFM) layer 14, a conventional pinned, or reference layer 16 having a magnetic moment 17, a conventional tunneling barrier layer 18, a conventional free layer 20, and a conventional capping layer 22. Also shown is top contact 24. Top and bottom contacts may be coupled to the selection device 62 depicted in FIG. 2.
The conventional STT-RAM 50 includes a conventional magnetic storage cell 60 including the conventional MTJ 10 and a selection device 62. The selection device 62 is generally a transistor such as a NMOS transistor and includes a drain 66, a source 64, and a gate 68. Also depicted are a word line 72, a bit line 74, and source line 70. The word line 72 is oriented perpendicular to the bit line 74. The source line 70 is typically either parallel or perpendicular to the bit line 74, depending on specific architecture used for the conventional STT-RAM 1. The bit line 74 is connected to the MTJ 10, while the source line 70 is connected to the source 64 of the selection device 62. The word line 72 is connected to the gate 68.
The conventional STT-RAM 50 programs the magnetic memory cell 60 by driving a bi-directional current through the cell 60. In particular, the MTJ 10 is configured to be changeable between high and low resistance states by a current flowing through the conventional MTJ 10. For example, the MTJ 10 may be a magnetic tunneling junction (MTJ) or other magnetic structure that may be written using the spin transfer effect. Typically, this is achieved by ensuring that the MTJ 10 has, for example, a sufficiently small cross-sectional area as well as other features desirable for switching using the spin transfer effect. When the current density is sufficiently large, the current carriers driven through the MTJ 10 may impart sufficient torque to change the state of the MTJ 10. When the write current, such as Iw1, is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current, such as Iw2, is passed through the MTJ 10 in the opposite direction, the state may be changed from a high resistance state to a low resistance state.
During write operations, the word line 72 is high and turns on the selection device 62. The write current flows either from the bit line 74 to the source line 70, or vice versa, depending upon the state to be written to the magnetic memory cell 60. The magnetic moment 21 of the conventional free layer 20 may thus be changed. During read operations, the column decoder (not shown) selects the desired bit lines 74. A row decoder (not shown in FIG. 2) also enables the appropriate word line(s) 72. Thus, the word line 72 is high, enabling the selection device 62. Consequently, a read current flows from the bit line 74 to the source line 70. In addition to the read current (IData in FIG. 2) flowing through the cell being read, reference currents are also driven through reference resistors (not shown in FIG. 2). The output signals are provided to a sense amplifier (not shown).
Although the conventional MTJ 10 and STT-RAM 50 may be written using spin transfer and used in an STT-RAM, there are drawbacks. For example, the write error rates may be higher than desired for memories having an acceptable pulse width. The write error rate (WER) is the probability that the cell 60 (i.e. the magnetization 21 of free layer 20 of the conventional magnetic junction) is not switched when subjected to a current that is at least equal to the typical switching current. The WER is desired to be 10−9 or less. WER of 10−21 is desired to be compatible with DRAM. However, very high currents can be required to achieve switching of the conventional free layer 20 at this WER value. In addition, it has been determined that the WER may be challenging to improve for shorter write current pulses. For higher pulse widths, the WER versus voltage applied to the MTJ 10 has a higher slope. Thus, application of a higher voltage for the same pulse width may bring about a significant reduction in the WER. However, as the pulse widths shorten, the slope of the WER curves decreases. For a decreasing pulse width, an increase in voltage and/or current is less likely to bring about a reduction in the WER. At sufficiently short pulses, even high voltages/currents do not result in a lower error rate. Consequently, memories employing the conventional MTJ 10 may have unacceptably high WER that may not be cured by an increase in voltage.
Furthermore, although a single magnetic tunneling junction is shown in FIG. 1, dual magnetic tunneling junctions are often used to obtain a sufficiently high spin transfer torque for switching. The dual magnetic tunneling junction has a single free layer sandwiched by two tunneling barrier layers. Each tunneling barrier layer is between the free layer and a reference layer. The second (upper) tunneling barrier of a dual magnetic tunneling junction may be challenging to grow with a suitable crystal structure. Further, to obtain such a high torque the reference layers have their magnetic moments fixed in opposite directions. As a result, there is cancellation of magnetoresistance, which lowers the read signal. Such a reduction in signal is undesirable.
Moreover, it is desirable to provide an STT-RAM that is scalable and has sufficiently fast access times to continue development as a next-generation nonvolatile memory. Providing such a memory given the challenges described above may be difficult or impossible.
Accordingly, what is needed is a method and system that may improve the performance of the spin transfer torque based memories. The method and system described herein address such a need.